1. Field of the Invention
The present invention relates to a CMOS structure and method utilizing decreased lateral resistance to prevent latchup and, more particularly, to a CMOS structure which utilizes proton bombardment to decrease the n-tub lateral resistivity which results in significantly reducing latchup.
2. Description of the Prior Art
A generic problem associated with CMOS structures has been their vulnerability to an undesirable conduction mechanism known as latchup. Latchup is a condition where high currents are conducted between VDD and VSS, which can cause the IC to cease functioning and even be destroyed. In particular, it is known that CMOS integrated circuits commonly contain parasitic PNPN structures which can give rise to the undesired latchup condition via an SCR action wherein the device is turned on by forward biasing one of the junctions in the PNPN structure. The device remains "on" even after the signal which produced the forward biasing is removed, and this can lead to destruction of the device by excessive current flow. The current gains of the parasitic npn and pnp transistors are the key parameters to control in avoiding latchup. If the product of the current gains of the two devices exceeds unity, the device can latch. Several techniques have been used to lower the current gains of the two devices, including gold doping and neutron irradiation to reduce the minority-carrier lifetimes. These and other methods of reducing latchup are discussed in the article "Latchup Control in CMOS Integrated Circuits", by A. Ochoa et al, appearing in IEEE Transactions in Nuclear Science, Vol. NS-26, No. 6, Dec. 1979 at pp. 5056-5058. These techniques are difficult to control and cause other deleterious effects in device operation (excess leakage, for example).
U.S. Pat. No. 4,203,126 issued to E. W. Yim et al on May 13, 1980, describes an alternative technique which utilizes a retarded electric field for reducing the current gain in the base region of the parasitic transistors in the CMOS device, thereby increasing the level of current required to produce latchup. The Yim et al method, however, requires additional masking steps early in the formation of the device which results in creating pattern shift and adding extra processing time and expenses to the final device. Another method of reducing latchup is disclosed in U.S. Pat. No. 4,327,368 issued to Y. Uchida on Apr. 27, 1982. In order to minimize latchup, a reverse-biased voltage is applied to the substrate via a metal plate which is connected between the bottom of the substrate and the power supply. Although this method is successful, its use in association with complementary MOS technology, which includes both n-and p-type devices in the same substrate, is suspect.
Recently, it has been found that the use of n-well epi-CMOS structures in place of the standard p-well reduces the latchup sensitivity. A discussion of this phenomenon can be found in the article entitled "Latchup Prevention Using an N-Well Epi-CMOS Process", by P. J. Holly et al., appearing in IEEE Transactions on Electron Devices, Vol. ED-30, No. 10, October 1983, at pp. 1403-1405. Although the use of an n-epi structure does reduce latchup, many circuits are formed using either a p-well or "twin" (both n and p) well structure, where latchup remains a major problem. Therefore, there is still a need for a method of reducing latchup in these conventional circuit structures.